In general, the term "domino logic" is used to refer to an arrangement of logic circuit stages which may, for example, be cascaded together in an integrated circuit array configuration. A signal may be input to a first stage where it is evaluated in order to provide an output signal to a second stage where that output signal is again evaluated to provide an output signal for propagation to and evaluation by yet another stage in the circuit. Thus a "domino" effect is achieved whereby signals are sequentially propagated through an array of "stages" or "domino blocks", and each successive stage performs an evaluation of an input condition until a final output is provided at a final output stage.
Domino logic circuits may be arranged so that signals can propagate through the various stages without being separately clocked at each stage. Accordingly, a domino arrangement allows a signal to be processed through a relatively complex logic function during a single clock cycle. This ability of a domino circuit obviates the need for plural clock cycles to process the input signals, and also decreases the overall processing time of the logic function.
Further, domino logic arrangements have not been applicable to all logic implementations. For example, in MOS technology, a positive logic scheme cannot be maintained since a typical adder circuit requires the use of negative logic functions such as NAND, NOR and NOT functions. Typical MOS logic implementations are limited to positive or non-inverting logic schemes which use only positive functions such as AND gates and OR gates.
Perhaps the biggest disadvantage to domino logic is that it is not a complete logic family, i.e. it is not possible to construct all logic functions using only domino circuits or blocks. The problem is that domino logic, as hereinbefore explained, does not admit any inverting stages. Attempts to avoid this "inversion" problem by adding inverting stages to ordinary domino logic introduce signal race conditions which would not be present in a pure domino logic configuration. The term "race condition" characterizes a timing relation between two signals that must be met for the circuit to function correctly and reliably, and this race condition is not relaxed by slowing the clock frequency.
In the past, efforts have been made to overcome the inversion problem, but such efforts have not been totally successful. Such an example would be where the clock signal to the domino logic block is delayed in order to prevent the domino block from evaluating until the negative input to the block has stabilized. However, if the delay introduced in the clock is not large enough, a race condition is introduced and the circuit will fail to function properly and reliably, and any extra delay of the clock, which may be applied as a safety margin, will slow down the evaluation function of the circuit by an equal amount.
Thus, there is a need to provide an improved method and apparatus for the implementation of domino logic configurations which include inverting stages but which, at the same time do not introduce signal race conditions which may otherwise adversely affect the timing and reliability of the logic circuitry.